VHDL and other hardware description
languages ( 28 ) :
Hardware description languages are essential tools for
handlingthe increasing complexity of the hardware
designs.Information on VHDL hardware description language that is
usedfor designing logic circuits implemented with FPGA or ASIC
technologies.VHDL is a way of describing the desired operation of a
logic device. Although it is a standard, vendors all choose
different parts to implement and add their own quirks.In VHDL
synthesis, we describe a program that would have the same behavior
as the circuit we wish to create. This program is used by the
synthesis tools to create the configuration file that will configure
the specific FPGA or PLD into a correct circuit. The syntax is very
similar to Ada.
General
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Design and Reuse Web site
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Getting a handle on HDLs - Programmable-logic chips and
designs are growing more complex. As a result, you?ll sooner or
later need to add HDL expertise to your skills if you want to keep
hitting those project deadlines. For this Hands-On Project, I
learn VHDL, complete a mixed logic and embedded-memory design in
an FPGA, and share observations along the way.
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Interfacing HDLs with conventional programming languages -
programming languages that interface with HDL models facilitate
hardware/software codesign
VHDL
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10 tips for generating reusable VHDL - Your ability to reuse
blocks expressed in an HDL is critical to designing systems on
chips. Here are some tips you can use to generate VHDL-based
blocks that you and others can reuse in subsequent chip designs.
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HDL basic training: top-down chip design using Verilog and VHDL
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Using VHDL-AMS to model complex heterogeneous systems, part 1
- HDLs bridge the gap between math-based tools and physics-based
tools to help you meet model-development requirements.
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Using VHDL-AMS to model complex heterogeneous systems, part 2
- You can implement DSP-controller algorithms using the
mixed-signal features of the VHDL-AMS modeling language.
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VHDL and Verilog fundamentals--expressions, operands, and
operators - data objects in VHDL and Verilog form expression
operands, knowing the operand differences between the two HDLs
helps you write more efficient chip-design code
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VHDL and Verilog fundamentals--design entities, data types, and
data objects
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VHDL emerges as a commercial design tool - despite the initial
challenges imposed by VHDL, the language, born of the military,
has made the commercial sector sit up and take notice
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VHDL Synthesis Tutorial
Verilog
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Simulating mixed-mode designs with Verilog-only models - PLL
circuits offer developers of mixed-signal designs a unique
challenge. Commonly used as frequency synthesizers, clock
multipliers, or clock-recovery devices, PLLs are crucial to many
microcontrollers and microprocessors. As more functions enter the
digital domain, verification becomes more difficult and requires
more sophisticated models. A Verilog-only model can solve most of
these problems.
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The C Programmers Guide to Verilog - Now that hardware is
designed in high-level languages, the fields of hardware and
software development are beginning to merge. Here's an
introduction to hardware design in Verilog for the uninitiated.
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Verilog FAQ
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Verilog Behavioral Simulator - software for Verilog simulation
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HDL basic training: top-down chip design using Verilog and VHDL
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VHDL and Verilog fundamentals--expressions, operands, and
operators - data objects in VHDL and Verilog form expression
operands, knowing the operand differences between the two HDLs
helps you write more efficient chip-design code
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VHDL and Verilog fundamentals--design entities, data types, and
data objects
Other languages
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CynApps Cynlib - C++ based hardware description language
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LavaLogic - Java-based synthesis tool
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SpecC
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Superlog - superset of Verilog, borrows features from VHDL and
C++
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SystemC - modeling platform that enables, promotes and
accelarates system-level co-design and IP exchange
Organizations
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